The present invention relates to a video signal processing system comprising a display output module for digitally processing a video signal that is controlled by a host CPU.
Traditionally, a display output module for handling a digital video signal has been controlled in central processing performed by a host CPU.
When the host CPU updates display setting data, the updated data should be inputted into the display output module during a non-display period. The non-display-period can be identified by using a vertical sync signal.
If display setting data were changed during a display period, then that would be perceived by a user as degradation in image quality or screen flickering, because the display settings are immediately reflected in the display output module. As solutions to this problem, digital signal processing circuit controllers are disclosed in Japanese Patent Laid-Open No. 63-143590 and Japanese Patent No. 2752082.
The technology disclosed in Japanese Patent Laid-Open No. 63-143590 provides the following configuration.
A display output module includes first display setting registers, second display setting registers, a display processing circuit, and an enable bit indicating that the second display setting register is update-enabled. A host CPU negates the enable bit when data is written into the first display setting registers.
Then, changes to display settings are sequentially written into the first display setting registers. After the display settings are written into the first registers, the enable bit is asserted.
When the enable bit is asserted and a vertical sync signal indicates a non-display period, the second display setting register is loaded with an output from the first display setting registers and outputs it to the display processing circuit.
FIGS. 18 and 19 shows a technology disclosed in Japanese Patent No. 2752082.
As shown in FIG. 18, a display output module includes flip-flops 323-325, which are first display setting registers, flip-flops 327-329, which are second display setting registers, and a digital video signal processing circuit 326, which is a display processing circuit. A microcomputer 321, which is a host CPU, inputs a vertical sync signal to change display settings and updates values in the first display setting registers in one vertical synch signal period.
The inputs of the second display setting registers are connected to the outputs of the first display setting registers. The second display setting registers are loaded with outputs from the first display setting registers in synchronization with the vertical sync signal and output it to the display processing circuit.
The microcomputer 321 and a decoder 322 in FIG. 18 are interconnected through a bus 330 to send and receive control data and address data to and from each other. The D-flip-flops 323, 324, and 325 are connected with the decoder 322 through a data line 331 and receive the control data and receive a selection signal through signal lines 332A, 332B, and 332C.
Symbol xe2x80x9caxe2x80x9d in FIG. 19 indicates the vertical sync signal, xe2x80x9cVxe2x80x9d indicates a vertical synch signal period, and xe2x80x9c1Vxe2x80x9d indicates a vertical scan period. Symbol xe2x80x9cbxe2x80x9d indicates an operation of the microprocessor 321, symbols xe2x80x9ccxe2x80x9d, xe2x80x9cdxe2x80x9d, and xe2x80x9cexe2x80x9d indicate an operation of the D-flip-flops 323, 324, and 325, respectively, and symbols xe2x80x9cfxe2x80x9d, xe2x80x9cgxe2x80x9d, and xe2x80x9chxe2x80x9d indicate operations of the D-flip-flops 327, 328, 329, respectively.
Period 341 indicated by xe2x80x9cbxe2x80x9d in FIG. 19 is a preparation period. The preparation is for setting control data and address data in a predetermined register of the microcomputer 321. Period 342 is for monitoring an incoming vertical sync signal and, when the vertical sync signal is detected, obtaining it. Thus, the microcomputer 321 can know the point of the vertical sync signal.
FIG. 19 shows a timing chart, in which symbol xe2x80x9callxe2x80x9d indicates control data transferred to D-flip-flop 323 together with address data at address A, xe2x80x9cbxe2x80x9d indicates control data transferred to D-flip-flop 324 together with address data at address B, and xe2x80x9ccxe2x80x9d indicates control data transferred to D-flip-flop 325 together with address C. The time chart shows the transfer of data A, a, B, b, and C, c mentioned above.
As described above, display setting data input into the display processing circuit is updated with the timing of a vertical sync signal in either of these control methods for display setting.
However, the above-described prior arts have the following problems.
The first problem is that the host CPU must generate an interrupt to input the vertical sync signal or means such as polling to a flag in which the vertical sync signal is reflected in order for the host CPU to control the generation or modification of display setting data.
In particular, the vertical sync signal is not associated with display setting changes in the display setting control method described in Japanese Patent Laid-Open No. 63-143590. In a video signal processing system that requires frequent display setting changes, there is the likelihood that the host CPU cannot know a display setting change and the next display setting change occurs before the host CPU detects the display setting change and, as a result, a plurality of display setting changes are made in one display period starting with a vertical sync signal and only the last display setting change is reflected on display. To avoid this problem, the host CPU must perform control in synchronization with the vertical sync signal.
The second problem is that the cycle for a change to display setting data must be started by the host CPU in synchronization with the vertical sync signal and the change must be made in a non-display period.
Specifically, an embodiment of the display setting control method is described in Japanese Patent No. 2752082 in which a host CPU inputs the vertical sync signal as an interrupt signal to prepare update data to be placed in the first display setting register and starts a write access to the first display setting register.
As shown at bxe2x80x2 in FIG. 19, however, if the vertical sync signal makes a transition during the access by the host CPU for changing the display setting data, a part of display setting data to be changed is not updated before a display period starts, thus the display output module outputs display setting data being updated together with updated display setting data.
While proper display setting data is displayed eventually after a number of vertical sync signal transitions take place and all display setting data is settled, degraded image quality is provided during progress of the update.
To address this problem, a method has been disclosed for dividing the vertical sync signal to prolong a display setting update interval.
However, this control method cannot ensure that display setting changes are made at once in a system in which the amount of display setting data is very large because of diversified digital signal processing, a system in which an application is running under an operating system and display setting register change time is unpredictable from the application due to another task, or a system having an internal configuration in which access from the host CPU to a display setting register is not immediately reflected.
A requirement common to the first and second problems is that the host CPU must monitor a vertical sync signal in controlling display setting. Therefore, the execution of an application software program is interrupted by the vertical sync signal, degrading the performance of the system.
There is another problem that because only a part of display setting data is changed or different display setting data changes are periodically performed and the data must be set by the host CPU in the display module each time a change is made, the number of cycles consumed by a host CPU for controlling a display output module is increased.
It is an object of the present invention to provide a video signal processing system that can ensure that display settings are updated at a time and can synchronize the display settings with display outputs without degrading the performance of the system.
It is another object of the present invention to provide a video signal processing system that can improve versatility concerning video setting changes made by a host CPU.
The present invention set forth in claim 1 provides a video signal processing system provided between a host CPU and a monitor to update display setting data by the CPU, the video signal processing system comprising: a first display setting register mapped into an address space for temporarily holding various display setting data under the control of a write control signal, the display setting data being generated and outputted asynchronously with a vertical sync signal; a decoder for generating the write control signal associated with the first display setting register for address access; a second display setting register into which an output from the first display setting register is inputted for updating data held in the second display setting register in synchronization with a first control signal; a display output module for performing digital processing of a video display signal according to an output from the second display setting register; and a display setting start flag register in which a display setting start flag generated and outputted asynchronously with the vertical sync signal is set; wherein the first control signal is generated by using the vertical sync signal and an output from the display setting start flag register and a display setting end flag register is provided for notifying the host CPU of the completion of update of the second display setting register.
The present invention set forth in claim 2 provides a video signal processing system provided between a host CPU and a monitor to update display setting data by the CPU, and the video signal processing system comprising: first display setting registers and second display setting registers mapped into an address space for temporarily holding various display setting data under the control of write control signals, the display setting data being generated asynchronously with a vertical sync signal; a decoder for generating the write control signals associated with the plurality of first and second display setting registers for address access; selectors for switching between outputs according to an input, the input being a pair of outputs of the first and second display setting registers; a display output module for performing digital signal processing of a video display signal according to an output from the selector; and a selector selection signal generator for controlling the switching performed by the selectors, the selector selection signal generator comprising a display control register having a first and second fields for temporarily holding display control information generated and outputted asynchronously with a vertical sync signal, and a flip-flop for holding an output from the second field with the timing of the vertical sync signal and the first field; wherein the switching performed by the selectors is controlled by an output signal from the flip-flop and display setting control data is set in the first and second fields under the control of a write strobe line, the write strobe line being the output of the decoder.
The present invention set forth in claim 3 provides the video signal processing system according to claim 1, comprising a display control index register having fields corresponding to each of the plurality of second display setting registers into which an output from the first display setting registers is inputted for updating data held in the second display setting register in synchronization with a first control signal, wherein the first control signal corresponding to each of the plurality of second display setting registers is generated by using an output form the display control index register and the vertical sync signal, and the second display setting registers are updated by the first control signal.
The present invention set forth in claim 4 provides the video signal processing system according to claim 2, comprising a display control index register having fields, each of the fields corresponding to each of the plurality of selectors, wherein the first control signals corresponding to the plurality of selectors are generated by using an output form the display control index register and the vertical sync signal, and the selectors select and provide the output of the first display setting register or the output of the second display setting registers according to the first control signals.
The present invention set forth in claim 5 provides a video signal processing system provided between a host CPU and a monitor to update display setting data by the CPU, the video signal processing system comprising: a plurality of pairs of first display setting register and second display setting register, each of the pairs being assigned to one address; a decoder for generating a plurality of write control signals associated with the plurality of pairs for address access; a display control register for temporarily holding display control information externally generated and outputted asynchronously with a vertical sync signal; and a plurality of selectors for selecting an output from among outputs of the first display setting registers and the second display setting registers inputted into the selectors and outputting the output to a display output module; wherein the first and second display setting registers select and hold display setting data generated by a host CPU asynchronously with the vertical sync signal according to the first control signal and the write control signals; the selectors select the output from among the outputs of the first display setting registers and the second display setting registers and output the selected output to the display output module in synchronization with a second control signal; and the first and second control signals are generated by using the vertical sync signal and an output from the display control register.
The present invention set forth in claim 6 provides the video signal processing system according to any of claims 2, 4, and 5, comprising means for providing information about input switching performed by the plurality of selectors to an external element.
The present invention set forth in claim 7 provides a video signal processing system provided between a host CPU and a monitor to update display setting data by the CPU, the video signal processing system comprising: a plurality of first display setting registers mapped into an address space for temporarily holding various display setting data externally generated and outputted asynchronously with a vertical sync signal under the control of a write control signal; display setting start flag register in which a display setting start flag indicating the completion of access to the plurality of first display setting registers is set, the display setting start flag being externally set asynchronously with the vertical sync signal; a register setting controller for performing register access by using the display setting start flag and vertical sync signal; a plurality of second display setting registers mapped into an address space for holding the display setting data under the control of a write control signal, the data being updated by the register setting controller; a decoder for generating a plurality of the write control signals corresponding to the plurality of second display setting registers for address access; a display setting end flag indicating the completion of update of the second display setting registers; and a display output module for performing digital processing of a video display signal according to an output from the plurality of second display setting registers; wherein the register setting controller uses data in the plurality of first display setting registers to update the plurality of second display setting registers during a vertical synchronization period.
The present invention set forth in claim 8 provides a video signal processing system provided between a host CPU and a monitor to update display setting data by the CPU, the video signal processing system comprising: a plurality of first display setting registers mapped into an address space for temporarily holding various display setting data externally generated and outputted asynchronously with a vertical sync signal under the control of a write control signal; a frame count detector for providing an output indicating whether the current frame matches a frame count in a frame count setting register; a register setting controller performing register access by using a display setting start flag indicating the completion of access to the plurality of first display setting registers and the vertical sync signal, the display setting start flag being externally set asynchronously with the vertical sync signal; a plurality of second display setting registers mapped into an address space for holding the display setting data under the control of a write control signal, the data held in the plurality of second display setting registers being updated by the register setting controller; a decoder for generating a plurality of the write control signals corresponding to the plurality of second display setting registers for address access; and a display setting end flag indicating the completion of update of the second display setting registers; display output module for performing digital processing of a video display signal according to an output from the plurality of second display setting registers wherein, the frame count detector comprises: a frame count setting register externally set asynchronously with the vertical sync signal for indicating update intervals of the plurality of first display setting registers; a frame counter for counting frames by using the vertical sync signal; and a comparator for comparing an output from the frame count setting register with an output from the frame counter to determine whether the current frame matches the frame count in the frame count setting register, wherein, the register setting controller and the frame count detector are constituted so that the register setting controller initializes the frame counter according to a setting in the display setting start flag and the frame count detector holds the frame counter and provides the vertical sync signal to the register setting controller until the display setting end flag is set after the output from the frame counter matches the output from the frame count setting register.
The present invention set forth in claim 9 provides a video signal processing system provided between a host CPU and a monitor to update display setting data by the CPU, the video signal processing system comprising: a plurality of first display setting registers mapped into an address space for temporarily holding various display setting data under the control of a write control signal, the display setting data being externally generated and outputted asynchronously with a vertical sync signal; a display setting start flag register in which a display setting start flag indicating the completion of access to the plurality of first display setting registers is set, the display setting start flag being externally set asynchronously with the vertical sync signal; a display setting selection register for indicating that the nth set of ones of the plurality of first display setting registers is used, the display setting selection register being externally set asynchronously with the vertical sync signal; a register setting controller for performing register access by using the display setting start flag and vertical sync signal; a plurality of second display setting registers mapped into an address space for holding the display setting data under the control of a write control signal, the data held in the plurality of second display setting registers being updated by the register setting controller; a decoder for generating a plurality of the write control signals corresponding to the plurality of second display setting registers for address access; and a display output module for performing digital processing of a video display signal according to an output from the plurality of second display setting registers; wherein, the first display setting registers are capable of holding a plurality of sets of data held in the second display setting registers; and the register setting controller uses data in a plurality of ones of the first display setting registers according to data set in the display setting selection register to update the second display setting registers.
The present invention set forth in claim 10 provides a video signal processing system provided between a host CPU and a monitor to update display setting data by the CPU, the video signal processing system comprising: a first display setting register mapped into an address space for temporarily holding various display setting data under the control of a write control signal, the display setting data being externally generated and outputted asynchronously with a vertical sync signal; a display setting start flag register in which a display setting start flag indicating the completion of access to the first display setting registers is set, the display setting start flag being externally set asynchronously with the vertical sync signal; register setting controller for performing register access by using the display setting start flag and vertical sync signal; a data bus used by the register setting controller and the host CPU for accessing the first display setting register; a data bus arbiter for controlling the use of the data bus; a second display setting registers mapped into an address space for holding the display setting data under the control of a write control signal, the data held in the plurality of second display setting registers being updated by the register setting controller; a decoder for generating a plurality of the write control signals corresponding to the plurality of second display setting registers for address access; and a display output module for performing digital processing of a video display signal according to an output from the plurality of second display setting registers; wherein the data bus arbiter is constituted so as to change the bus priority of the register setting controller to the highest priority in vertical synchronization periods.
The present invention set forth in claim 11 provides a video signal processing system provided between a host CPU and a monitor to update display setting data by the CPU, the video signal processing system comprising: a plurality of pairs of first display setting register and second display setting register, each of the pairs being assigned to one address; a decoder for generating a plurality of write control signals corresponding to the plurality of pairs for address access; a display control register for temporarily holding display control information externally generated and outputted asynchronously with a vertical sync signal; a plurality of selectors for selecting an output from among outputs from the first display setting registers and the second display setting registers inputted into the selectors and outputting the output to a display output module; wherein it is constituted so that the first and second display setting registers select and hold various display setting data generated asynchronously with the vertical sync signal by a host CPU according to the write control signals, a control signal generated by using an output of the display control register and the vertical sync signal; the selectors select the output from among the outputs from the first display setting registers and the second display setting registers and output the selected output to a display output module in synchronization with the vertical sync signal and the control signal generated by using the output of the display control register; and the first and second display setting registers are mutually exclusively selected to be updated by the host CPU and the first and second display setting registers are mutually exclusively selected by the selectors.